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| INTEGRATED CIRCUITS DATA SHEET UDA1330ATS Low-cost stereo filter DAC Product specification Supersedes data of 2000 April 18 File under Integrated Circuits, IC01 2001 Feb 02 Philips Semiconductors Product specification Low-cost stereo filter DAC FEATURES General * Low power consumption * Power supply voltage from 2.7 to 5.5 V * Selectable control via L3 microcontroller interface or via static pin control * System clock frequencies of 256fs, 384fs and 512fs selectable via L3 interface or 256fs and 384fs via static pin control * Supports sampling frequencies (fs) from 8 to 55 kHz * Integrated digital filter plus non inverting Digital-to-Analog Converter (DAC) * No analog post filtering required for DAC * Slave mode only applications * Easy application * Small package size (SSOP16) * TTL tolerant input pads * Pin and function compatible with the UDA1320ATS. Multiple format input interface * L3 mode: I2S-bus, MSB-justified or LSB-justified 16, 18 and 20 bits format compatible * Static pin mode: I2S-bus and LSB-justified 16, 18 and 20 bits format compatible * 1fs input format data rate. DAC digital sound processing * Digital logarithmic volume control in L3 mode * Digital de-emphasis for 32, 44.1 and 48 kHz sampling frequencies in L3 mode or 44.1 kHz sampling frequency in static pin mode * Soft mute control both in static pin mode and L3 mode. Advanced audio configuration * Stereo line output (volume control in L3 mode) * High linearity, wide dynamic range and low distortion. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UDA1330ATS SSOP16 DESCRIPTION UDA1330ATS APPLICATIONS * PC audio applications * Car radio applications. GENERAL DESCRIPTION The UDA1330ATS is a single-chip stereo DAC employing bitstream conversion techniques. The UDA1330ATS supports the I2S-bus data format with word lengths of up to 20 bits, the MSB-justified data format with word lengths of up to 20 bits and the LSB-justified serial data format with word lengths of 16, 18 and 20 bits. The UDA1330ATS can be used in two modes: L3 mode or the static pin mode. In the L3 mode, all digital sound processing features must be controlled via the L3 interface, including the selection of the system clock setting. In the two static modes, the UDA1330ATS can be operated in the 256fs and 384fs system clock mode. Muting, de-emphasis for 44.1 kHz and four digital input formats (I2S-bus or LSB-justified 16, 18, and 20 bits) can be selected via static pins. The L3 interface cannot be used in this application mode, so volume control is not available in this mode. VERSION SOT369-1 plastic shrink small outline package; 16 leads; body width 4.4 mm 2001 Feb 02 2 Philips Semiconductors Product specification Low-cost stereo filter DAC QUICK REFERENCE DATA SYMBOL Supplies VDDA VDDD IDDA DAC analog supply voltage digital supply voltage DAC analog supply current VDDA = 5.0 V operating power-down VDDA = 3.3 V operating power-down IDDD Tamb Vo(rms) (THD + N)/S S/N cs Vo(rms) (THD + N)/S S/N cs P digital supply current ambient temperature output voltage (RMS value) total harmonic distortion-plus-noise to signal ratio signal-to-noise ratio channel separation output voltage (RMS value) total harmonic distortion-plus-noise to signal ratio signal-to-noise ratio channel separation note 1 at 0 dB at -60 dB; A-weighted code = 0; A-weighted note 1 at 0 dB at -60 dB; A-weighted code = 0; A-weighted VDDD = 5.0 V VDDD = 3.3 V Digital-to-analog converter (VDDA = VDDD = 5.0 V) - - - - - - - - - - playback mode VDDA = VDDD = 5.0 V VDDA = VDDD = 3.3 V Note 1. The output voltage scales linearly with the power supply voltage. - - 75 33 - - - - -40 - - 2.7 2.7 PARAMETER CONDITIONS MIN. UDA1330ATS TYP. MAX. UNIT 5.0 5.0 9.5 400 7.0 250 5.5 3.0 - 1.45 -90 -40 100 100 1.0 -85 -38 100 100 5.5 5.5 - - - - - - +85 - -85 -35 95 - - - - - - V V mA A mA A mA mA C V dB dB dB dB V dB dB dB dB Digital-to-analog converter (VDDA = VDDD = 3.3 V) Power dissipation power dissipation - - mW mW 2001 Feb 02 3 Philips Semiconductors Product specification Low-cost stereo filter DAC BLOCK DIAGRAM UDA1330ATS handbook, full pagewidth VDDD 4 1 2 3 VSSD 5 7 11 10 9 8 APPSEL APPL0 APPL1 APPL2 APPL3 BCK WS DATAI DIGITAL INTERFACE CONTROL INTERFACE UDA1330ATS VOLUME/MUTE/DE-EMPHASIS 6 SYSCLK INTERPOLATION FILTER NOISE SHAPER VOUTL 14 DAC DAC 16 VOUTR 13 VDDA 15 VSSA 12 Vref(DAC) MGL401 Fig.0 Fig.1 Block diagram. PINNING SYMBOL BCK WS DATAI VDDD VSSD SYSCLK APPSEL APPL3 APPL2 APPL1 APPL0 Vref(DAC) VDDA VOUTL VSSA VOUTR 2001 Feb 02 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION bit clock input word select input handbook, halfpage data input digital supply voltage digital ground system clock input: 256fs, 384fs and 512fs application mode select input application input 3 application input 2 application input 1 application input 0 DAC reference voltage analog supply voltage for DAC left channel output analog ground right channel output 4 BCK 1 WS 2 DATAI 3 VDDD 4 UDA1330ATS VSSD 5 SYSCLK 6 APPSEL 7 APPL3 8 MGL402 16 VOUTR 15 VSSA 14 VOUTL 13 VDDA 12 Vref(DAC) 11 APPL0 10 APPL1 9 APPL2 Fig.2 Pin configuration. Philips Semiconductors Product specification Low-cost stereo filter DAC FUNCTIONAL DESCRIPTION System clock The UDA1330ATS operates in slave mode only. Therefore, in all applications the system devices must provide the system clock. The system frequency (fsys) is selectable and depends on the application mode. The options are: 256fs, 384fs and 512fs for the L3 mode and 256fs or 384fs for the static pin mode. The system clock must be locked in frequency to the digital interface input signals. The UDA1330ATS supports sampling frequencies from 8 to 55 kHz. Application modes The application mode can be set with the three-level pin APPSEL (see Table 1): * L3 mode * Static pin mode with fsys = 384fs * Static pin mode with fsys = 256fs. Table 1 Selecting application mode and system clock frequency via pin APPSEL MODE L3 mode static pin mode fsys 256fs, 384fs or 512fs 384fs 256fs UDA1330ATS In the L3 mode, pin APPL0 must be set to LOW. It should be noted that when the L3 mode is used, an initialization must be performed when the IC is powered-up. Multiple format input interface DATA FORMATS The digital interface of the UDA1330ATS supports multiple format inputs (see Fig.3). Left and right data-channel words are time multiplexed. The WS signal must have a 50% duty factor for all LSB-justified formats. The BCK clock can be up to 64fs, or in other words the BCK frequency is 64 times the Word Select (WS) frequency or less: fBCK 64 x fWS. Important: the WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital interface. The UDA1330ATS also accepts double speed data for double speed data monitoring purposes L3 MODE This mode supports the following input formats: * I2S-bus format with data word length of up to 20 bits * MSB-justified format with data word length up to 20 bits * LSB-justified format with data word length of 16, 18 or 20 bits. STATIC PIN MODE This mode supports the following input formats: * I2S-bus format with data word length of up to 20 bits * LSB-justified format with data word length of 16, 18 or 20 bits. These four formats are selectable via the static pin codes SF0 and SF1 (see Table 3). Table 3 Input format selection using SF0 and SF1 FORMAT I2S-bus LSB-justified 16 bits LSB-justified 18 bits LSB-justified 20 bits SF0 0 0 1 1 SF1 0 1 0 1 VOLTAGE ON PIN APPSEL VSSD 0.5VDDD VDDD The function of an application input pin (active HIGH) depends on the application mode (see Table 2). Table 2 Functions of application input pins FUNCTION PIN L3 MODE APPL0 APPL1 APPL2 APPL3 TEST L3CLOCK L3MODE L3DATA STATIC PIN MODE MUTE DEEM SF0 SF1 For example, in the static pin mode the output signal can be soft muted by setting pin APPL0 to HIGH. De-emphasis can be switched on for 44.1 kHz by setting pin APPL1 to HIGH; setting pin APPL1 to LOW will disable de-emphasis. 2001 Feb 02 5 Philips Semiconductors Product specification Low-cost stereo filter DAC Interpolation filter (DAC) The digital filter interpolates from 1fs to 128fs by cascading a recursive filter and an FIR filter (see Table 4). Table 4 Interpolation filter characteristics CONDITION 0 to 0.45fs >0.55fs 0 to 0.45fs VALUE (dB) 0.1 -50 108 Filter stream DAC UDA1330ATS ITEM Pass-band ripple Stop band Dynamic range Noise shaper The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC scales linearly with the power supply voltage. Pin compatibility In the L3 mode the UDA1330ATS can be used on boards that are designed for the UDA1320ATS. Remark: It should be noted that the UDA1330ATS is designed for 5 V operation while the UDA1320ATS is designed for 3 V operation. This means that the UDA1330ATS can be used with the UDA1320ATS supply voltage range, but the UDA1320ATS can not be used with the 5 V supply voltage. The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream DAC (FSDAC). 2001 Feb 02 6 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... ook, full pagewidth 2001 Feb 02 WS 1 BCK 2 3 LEFT >=8 1 2 3 DATA MSB B2 I2 WS 1 BCK 2 LEFT 3 >=8 1 2 MSB B2 S-BUS FORMAT DATA MSB B2 LSB MSB B2 WS LEFT BCK Philips Semiconductors Low-cost stereo filter DAC RIGHT >=8 MSB RIGHT 3 >=8 LSB MSB B2 MSB-JUSTIFIED FORMAT RIGHT 16 15 2 1 16 15 2 1 7 DATA MSB B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS WS LEFT 18 BCK 17 16 15 2 1 MSB B2 B15 LSB RIGHT 18 17 16 15 2 1 DATA MSB B2 B3 B4 B17 LSB LSB-JUSTIFIED FORMAT 18 BITS WS LEFT 20 BCK 19 18 17 16 15 2 1 RIGHT 20 19 18 17 16 15 2 1 MSB B2 B3 B4 B17 LSB UDA1330ATS DATA MSB B2 B3 B4 B5 B6 B19 LSB LSB-JUSTIFIED FORMAT 20 BITS MSB B2 B3 B4 B5 B6 B19 LSB MBL140 Product specification Fig.0 Fig.3 Digital interface input format data format. Philips Semiconductors Product specification Low-cost stereo filter DAC L3 INTERFACE The following system and digital sound processing features can be controlled in the L3 mode of the UDA1330ATS: * System clock frequency * Data input format * De-emphasis for 32, 44.1 and 48 kHz * Volume * Soft mute. The exchange of data and control information between the microcontroller and the UDA1330ATS is accomplished through a serial interface comprising the following signals: * L3DATA * L3MODE * L3CLOCK. Information transfer through the microcontroller bus is organized in accordance with the L3 interface format, in which two different modes of operation can be distinguished: address mode and data transfer mode. Address mode The address mode (see Fig.4) is required to select a device communicating via the L3 interface and to define the destination registers for the data transfer mode. Data bits 7 to 2 represent a 6-bit device address where bit 7 is the MSB. The address of the UDA1330ATS is 000101 (bit 7 to bit 2). If the UDA1330ATS receives a different address, it will deselect its microcontroller interface logic. Data transfer mode The selected address remains active during subsequent data transfers until the UDA1330ATS receives a new address command. Registers UDA1330ATS The fundamental timing of data transfers (see Fig.5) is essentially the same as the address mode. The maximum input clock frequency and data rate is 64fs. Data transfer can only be in one direction, consisting of input to the UDA1330ATS to program sound processing and other functional features. All data transfers are by 8-bit bytes. Data will be stored in the UDA1330ATS after reception of a complete byte. A multibyte transfer is illustrated in Fig.6. The sound processing and other feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data type that is transferred. This is performed in the address mode using bit 1 and bit 0 (see Table 5). Table 5 BIT 1 0 0 1 1 Selection of data transfer BIT 0 0 1 0 1 not used status (system clock frequency, data input format) not used TRANSFER data (volume, de-emphasis, mute) The second selection is performed by the 2 MSBs of the data byte (bit 7 and bit 6). The other bits in the data byte (bit 5 to bit 0) represent the value that is placed in the selected registers. The `status' settings are given in Table 6 and the `data' settings are given in Table 7. 2001 Feb 02 8 Philips Semiconductors Product specification Low-cost stereo filter DAC UDA1330ATS handbook, full pagewidth L3MODE th(L3)A tCLK(L3)L tsu(L3)A L3CLOCK tCLK(L3)H th(L3)A tsu(L3)A Tcy(CLK)(L3) tsu(L3)DA th(L3)DA L3DATA BIT 0 BIT 7 MGL723 Fig.4 Timing address mode. handbook, full pagewidth tstp(L3) tstp(L3) L3MODE tCLK(L3)L tsu(L3)D tCLK(L3)H Tcy(CLK)L3 th(L3)D L3CLOCK tsu(L3)DA th(L3)DA L3DATA WRITE BIT 0 BIT 7 MGL882 Fig.5 Timing data transfer mode. 2001 Feb 02 9 Philips Semiconductors Product specification Low-cost stereo filter DAC UDA1330ATS handbook, full pagewidth tstp(L3) L3MODE L3CLOCK L3DATA address data byte #1 data byte #2 address MGL725 Fig.6 Multibyte data transfer. Programming the features When the data transfer of type `status' is selected, the features for the system clock frequency and the data input format can be controlled. Table 6 BIT 7 0 1 Data transfer of type `status' BIT 6 0 0 BIT 5 SC1 0 BIT 4 SC0 0 BIT 3 IF2 0 BIT 2 IF1 0 BIT 1 IF0 0 BIT 0 0 0 REGISTER SELECTED SC = system clock frequency (2 bits); see Table 8 IF = data input format (3 bits); see Table 9 not used When the data transfer of type `data' is selected, the features for volume, de-emphasis and mute can be controlled. Table 7 BIT 7 0 0 1 1 Data transfer of type `data' BIT 6 0 1 0 1 BIT 5 VC5 0 0 0 BIT 4 VC4 0 DE1 0 BIT 3 VC3 0 DE0 0 BIT 2 VC2 0 MT 0 BIT 1 VC1 0 0 0 BIT 0 VC0 0 0 1 not used DE = de-emphasis (2 bits); see Table 10 MT = mute (1 bit); see Table 12 default setting REGISTER SELECTED VC = volume control (6 bits); see Table 11 2001 Feb 02 10 Philips Semiconductors Product specification Low-cost stereo filter DAC SYSTEM CLOCK FREQUENCY The system clock frequency is a 2-bit value to select the external clock frequency. Table 8 SC1 0 0 1 1 System clock settings SC0 0 1 0 1 512fs 384fs 256fs not used FUNCTION VOLUME CONTROL UDA1330ATS The volume control is a 6-bit value to program the volume attenuation from 0 to -60 dB and - dB in steps of 1 dB. Table 11 Volume settings VC5 0 0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 1 1 MUTE VC4 0 0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 1 1 VC3 0 0 0 0 : 0 0 0 0 0 1 1 1 1 1 1 1 1 VC2 0 0 0 0 : 0 1 1 1 1 0 0 0 0 1 1 1 1 VC1 0 0 1 1 : 1 0 0 1 1 0 0 1 1 0 0 1 1 VC0 0 1 0 1 : 1 0 1 0 1 0 1 0 1 0 1 0 1 -60 - -57 VOLUME (dB) 0 0 -1 -2 : -51 -52 -54 DATA FORMAT The data format is a 3-bit value to select the used data format. Table 9 IF2 0 0 0 0 1 1 1 1 Data input format settings IF1 0 0 1 1 0 0 1 1 IF0 0 1 0 1 0 1 0 1 I2S-bus LSB-justified 16 bits LSB-justified 18 bits LSB-justified 20 bits MSB-justified not used not used not used FORMAT DE-EMPHASIS De-emphasis is a 2-bit value to enable the digital de-emphasis filter. Table 10 De-emphasis settings DE1 0 0 1 1 DE0 0 1 0 1 FUNCTION no de-emphasis de-emphasis, 32 kHz de-emphasis, 44.1 kHz de-emphasis, 48 kHz Mute is a 1-bit value to enable the digital mute. Table 12 Mute setting MT 0 1 no muting muting FUNCTION 2001 Feb 02 11 Philips Semiconductors Product specification Low-cost stereo filter DAC LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDDD VDDA Txtal(max) Tstg Tamb Ves Isc(DAC) PARAMETER digital supply voltage analog supply voltage maximum crystal temperature storage temperature ambient temperature electrostatic handling voltage short-circuit current of DAC note 2 note 3 note 4 output short-circuited to VSSA(DAC) - output short-circuited to VDDA(DAC) - Notes 1. All supply connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor. 3. Equivalent to discharging a 200 pF capacitor via a 2.5 H series inductor. note 1 note 1 CONDITIONS - - - -65 -40 UDA1330ATS MIN. MAX. 6.0 6.0 150 +125 +85 +3000 +250 450 300 V V UNIT C C C V V mA mA -3000 -250 4. Short-circuit test at Tamb = 0 C and VDDA = 3 V. DAC operation after short-circuiting cannot be warranted. HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 190 UNIT K/W QUALITY SPECIFICATION In accordance with "SNW-FQ-611-E". 2001 Feb 02 12 Philips Semiconductors Product specification Low-cost stereo filter DAC UDA1330ATS DC CHARACTERISTICS VDDD = VDDA = 5.0 V; Tamb = 25 C; RL = 5 k; all voltages referenced to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL Supplies VDDA VDDD IDDA DAC analog supply voltage note 1 digital supply voltage note 1 operating power-down VDDA = 3.3 V operating power-down IDDD digital supply current VDDD = 5.0 V VDDD = 3.3 V Power dissipation P power dissipation playback mode VDDA = VDDD = 5.0 V - VDDA = VDDD = 3.3 V - VIH VIL ILI Ci VIH VIM VIL HIGH-level input voltage LOW-level input voltage input leakage current input capacitance VDDD = 5.0 V VDDD = 3.3 V VDDD = 5.0 V VDDD = 3.3 V 2.2 1.45 - - - - 0.9VDDD 0.4VDDD -0.5 75 33 - - - - - - - - - - - - - 0.8 0.5 1 10 mW mW - - - - 7.0 250 5.5 3.0 - - - - mA A mA mA DAC analog supply current VDDA = 5.0 V - - 9.5 400 - - mA A 2.7 2.7 5.0 5.0 5.5 5.5 V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Digital inputs: pins BCK, WS, DATAI, SYSCLK, APPL0, APPL1, APPL2 and APPL3 (note 2) V V V V A pF Three-level input: APPSEL HIGH-level input voltage MIDDLE-level input voltage LOW-level input voltage VDDD + 0.5 V 0.6VDDD +0.1VDDD V V 2001 Feb 02 13 Philips Semiconductors Product specification Low-cost stereo filter DAC UDA1330ATS SYMBOL DAC Vref(DAC) Io(max) Ro RL CL Notes PARAMETER CONDITIONS MIN. TYP. MAX. UNIT reference voltage maximum output current output resistance load resistance load capacitance with respect to VSSA (THD + N)/S < 0.1%; RL = 5 k 0.45VDDA - - 3 0.5VDDA 0.36 0.15 - - 0.55VDDA - 2.0 - 50 V mA k pF note 3 - 1. All supply connections must be made to the same external power supply unit. 2. The digital input pads are TTL compatible at 5 V, but the pads are not 5 V tolerant in the voltage range between 2.7 and 4.5 V. 3. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 must be used to prevent oscillations in the output operational amplifier. AC CHARACTERISTICS fi = 1 kHz; Tamb = 25 C; RL = 5 k; all voltages referenced to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL Vo(rms) Vo PARAMETER output voltage (RMS value) unbalance between channels at 0 dB at -60 dB; A-weighted code = 0; A-weighted CONDITIONS TYP. 1.45 0.1 -90 -40 100 100 1.0 0.1 at 0 dB at -60 dB; A-weighted code = 0; A-weighted fripple = 1 kHz; Vripple = 100 mV (p-p) -85 -38 100 100 60 - - -85 -35 95 - - - - - - - - MAX. V dB dB dB dB dB V dB dB dB dB dB dB UNIT Digital-to-analog converter (VDDA = VDDD = 5.0 V) (THD + N)/S total harmonic distortion-plus-noise to signal ratio S/N cs Vo(rms) Vo signal-to-noise ratio channel separation output voltage (RMS value) unbalance between channels Digital-to-analog converter (VDDA = VDDD = 3.3 V) (THD + N)/S total harmonic distortion-plus-noise to signal ratio S/N cs PSRR signal-to-noise ratio channel separation power supply ripple rejection 2001 Feb 02 14 Philips Semiconductors Product specification Low-cost stereo filter DAC UDA1330ATS TIMING VDDD = VDDA = 4.5 to 5.5 V; Tamb = -40 to +85 C; RL = 5 k; all voltages referenced to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL System clock (see Fig.7) Tsys system clock cycle time fsys = 256fs fsys = 384fs fsys = 512fs tCWL tCWH LOW-level system clock pulse width HIGH-level system clock pulse width fsys < 19.2 MHz fsys 19.2 MHz fsys < 19.2 MHz fsys 19.2 MHz Digital interface (see Fig.8) Tcy(BCK) tBCKH tBCKL tr tf tsu(DATAI) th(DATAI) tsu(WS) th(WS) Tcy(CLK)L3 tCLK(L3)H tCLK(L3)L tsu(L3)A th(L3)A tsu(L3)D th(L3)D tsu(L3)DA th(L3)DA tstp(L3) bit clock cycle time bit clock HIGH time bit clock LOW time rise time fall time data input set-up time data input hold time word select set-up time word select hold time 300 100 100 - - 20 0 20 10 - - - - - - - - - - - - - - - - - - - - - - 20 20 - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns 71 47 36 0.3Tsys 0.4Tsys 0.3Tsys 0.4Tsys 88 59 44 - - - - 488 325 244 0.7Tsys 0.6Tsys 0.7Tsys 0.6Tsys ns ns ns ns ns ns ns PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Control interface L3 mode (see Figs 4 and 5) L3CLOCK cycle time L3CLOCK HIGH time L3CLOCK LOW time L3MODE set-up time for address mode L3MODE hold time for address mode L3MODE set-up time for data transfer mode L3MODE hold time for data transfer mode L3DATA set-up time for data transfer and address mode L3DATA hold time for data transfer and address mode L3MODE stop time for data transfer mode 500 250 250 190 190 190 190 190 30 190 ns ns ns ns ns ns ns ns ns ns 2001 Feb 02 15 Philips Semiconductors Product specification Low-cost stereo filter DAC UDA1330ATS handbook, full pagewidth t CWH t CWL Tsys MGR984 Fig.7 System clock timing. handbook, full pagewidth WS th(WS) tf tsu(WS) tBCKH tr BCK tBCKL Tcy(BCK) DATAI tsu(DATAI) th(DATAI) MGL880 Fig.8 Serial interface timing. 2001 Feb 02 16 Philips Semiconductors Product specification Low-cost stereo filter DAC APPLICATION INFORMATION UDA1330ATS handbook, full pagewidth analog supply voltage R2 1 digital supply voltage R3 1 C1 100 F (16 V) C5 100 nF (63 V) VSSA system clock R1 47 BCK WS DATAI APPSEL SYSCLK 15 6 C6 100 nF (63 V) VDDA 13 5 VSSD 4 VOUTL C2 47 F (16 V) R5 10 k R4 100 left output VDDD 14 1 2 3 7 UDA1330ATS APPL0 APPL1 APPL2 APPL3 11 10 9 8 16 VOUTR C3 47 F (16 V) R7 10 k R6 100 right output 12 Vref(DAC) C7 100 nF (63 V) C4 47 F (16 V) MGL403 Fig.9 Application diagram. 2001 Feb 02 17 Philips Semiconductors Product specification Low-cost stereo filter DAC PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm UDA1330ATS SOT369-1 D E A X c y HE vM A Z 16 9 Q A2 pin 1 index A1 (A 3) Lp L A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.15 0.00 A2 1.4 1.2 A3 0.25 bp 0.32 0.20 c 0.25 0.13 D (1) 5.30 5.10 E (1) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.45 Q 0.65 0.45 v 0.2 w 0.13 y 0.1 Z (1) 0.48 0.18 10 0o o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT369-1 REFERENCES IEC JEDEC MO-152 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 2001 Feb 02 18 Philips Semiconductors Product specification Low-cost stereo filter DAC SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Manual soldering UDA1330ATS If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2001 Feb 02 19 Philips Semiconductors Product specification Low-cost stereo filter DAC Suitability of surface mount IC packages for wave and reflow soldering methods UDA1330ATS SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable 2001 Feb 02 20 Philips Semiconductors Product specification Low-cost stereo filter DAC DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development DEFINITIONS (1) UDA1330ATS This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Preliminary specification Qualification Product specification Production Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2001 Feb 02 21 Philips Semiconductors Product specification Low-cost stereo filter DAC NOTES UDA1330ATS 2001 Feb 02 22 Philips Semiconductors Product specification Low-cost stereo filter DAC NOTES UDA1330ATS 2001 Feb 02 23 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: Philips Hungary Ltd., H-1119 Budapest, Fehervari ut 84/A, Tel: +36 1 382 1700, Fax: +36 1 382 1800 India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260, Tel. +66 2 361 7910, Fax. +66 2 398 3447 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553 For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2001 Internet: http://www.semiconductors.philips.com SCA 71 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/05/pp24 Date of release: 2001 Feb 02 Document order number: 9397 750 07939 |
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